A QFN integrated circuit is a semiconductor device having a generally-rectangular (usually square) upper surface with electrical contacts along its edges. Existing techniques for packaging a QFN integrated circuit to produce a package make use of a leadframe produced by etching. The packaging technique is illustrated below with reference to FIG. 1, which shows a number of views parallel to the major plane of the QFN chip being mounted.
As shown in FIG. 1(a), in an initial step a leadframe having a diepad 1 and leads 3, 5 is positioned on a tape 7. It should be understood that FIG. 1(a) shows only a portion of the leadframe and the tape 7: both the tape 7 and leadframe extend laterally to an indefinite length to either side of the diagram. Die bonding is then performed to place a QFN die 9 onto diepad 1, as shown in FIG. 1(b).
Subsequently, as shown in FIG. 1(c), a wirebonding operation is performed to form wire bonds 11 between contacts on the upper surface of the die 9 and the leads 3, 5. Then, as shown in FIG. 1(d), a molding process is performed in which resin material 8 is formed encapsulating the die 9 and the leads 3, 5. Again, the resin material 8 extends laterally to either side of the figure. The resin material 8 is then cured. Then, as shown in FIG. 1(e), the tape 7 is removed, resulting in the structure of FIG. 1(f). At this stage, lead tape residues are removed by cleaning, and Ag plating is performed.
Then, as shown in FIG. 1(g), strip lamination is performed, resulting in a foil 6 on the side of the resin material 8 opposite the leadframe. Then as shown in FIG. 1(h) unit singulation is performed (this is shown schematically as slots 10 being formed in the resin material 8), to form individual package units 14.
As shown in FIG. 1(i), each singulated unit 14 is tested, using contact pins 13 (the foil 6 is omitted from the figure for simplicity). Then as shown in FIG. 1(j), it is picked up from foil 6 using a lifter unit 15 and a needle 16, and placed in a desired location for later use as shown in FIG. 1(k). Typically, this is on a reeled tape including flexible layers 18.
Note that the process above uses an etched leadframe. This is because conventional stamped leadframes cannot be used to produce leadframes with very tiny lead pitch (e.g., under 0.8 mm), since the leadframe punching tool would be easily broken. However, the use of the etched leadframes with small and/or custom designed lead pitch leads to a number of disadvantages.
Firstly, as the lead pitch becomes smaller, the cost of producing the etched leadframes is rising. Practically speaking, it is very difficult to produce an etched leadframe with a pitch less than 0.5 mm, and certainly very expensive to do so.
Secondly, since etched leadframes are usually pre-designed and etched at a specialist manufacturing location, making any modification of the design is logistically difficult, leading to rigidity in the process.
Thirdly, the presence of the tape 7 causes “lead bouncing,” which causes wire bonding difficulties such as bonded wire stress necks and crack stitches, and therefore marginal bonding reliability concerns.
Fourthly, taping the individual tiny leads 3, 5 causes mold resin bleeding and the issue of mold flashes. This may lead to a solderability failure.